kdrag.printers.verilog.to_verilog

kdrag.printers.verilog.to_verilog(modname: str, ins: list[ExprRef], outs: dict[ExprRef, ExprRef]) → str

Produces a pure combinatorial module in Verilog.

>>> x,y,z = smt.Consts("x y z", smt.BitVecSort(8))
>>> a,b,c = smt.Consts("a b c", smt.BoolSort())
>>> print(to_verilog("foo", [x, y], {a: smt.ULE(x + y, 17), z: x & y}))
// Generated by knuckledragger
module foo (
   input [7:0] x,
   input [7:0] y,
   output a,
   output [7:0] z
);
assign a = ((x + y) <= 8'd17);
assign z = (x & y);
endmodule

Parameters:

• modname (str)

• ins (list[ExprRef])

• outs (dict[ExprRef, ExprRef])

Return type:

str