VGA FPGA

 

Based on http://fpga4fun.com/PongGame.html

767 was the value checked for at 25Mhz. This is a count of 768.

I doubled it to 1535. and added one to all references to Counter X.

I am confused on these values. References I’m finding say to shoot for 31.5kHz but this works out to 32.5khz?

50e6/31.46875e3 gives 1588.87785501. Ok. That works too. I guess the monitor is just flexible.

 

 

 

 

I got an error for can’t use pin 101 which is V sync

This helped

http://www.alteraforum.com/forum/showthread.php?t=24974

Need to disable nCEO which is using that pin

 

module vga_test (
	output vga_h_sync,
	output vga_v_sync,
	output R,
	output G,
	output B,
	input clk
	
);


reg [10:0] CounterX;
reg [8:0] CounterY;
wire CounterXmaxed = (CounterX==1535);

always @(posedge clk)
if(CounterXmaxed)
  CounterX <= 0;
else
  CounterX <= CounterX + 1;

always @(posedge clk)
if(CounterXmaxed)
    CounterY <= CounterY + 1;
	 

reg vga_HS, vga_VS;
always @(posedge clk)
begin
  vga_HS <= (CounterX[10:5]==0);   // active for 16 clocks
  vga_VS <= (CounterY==0);   // active for 768 clocks
end

assign vga_h_sync = ~vga_HS;
assign vga_v_sync = ~vga_VS;


assign R =  CounterX[9];//CounterY[3] | (CounterX==256);
assign G = CounterX[8];//(CounterX[6] ^ CounterX[7]) | (CounterX==256);
assign B = CounterX[7]; //CounterX[5] | (CounterX==256);


endmodule

Alright. It appears to work. That is a good start.

I

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