Some simple FPGA stuff


Some articles and links of interest


State Machines

Becoming a State Machine Design Mastermind

Verilog IceStorm Series

Learning Verilog for FPGAs: The Tools and Building an Adder

Learning Verilog for FPGAs: Flip Flops

Opencores UART and PWM

Taking the Pulse (Width Modulation) of an FPGA


Xilinx FPGAs in C for Free

Bitonic Sort on FPGA

Sort Faster with FPGAs

FPGA motion planning

Manipulators get a 1000x FPGA-based speed bump


Gravity Simulations With An FPGA

The seller of the Cyclone IV RZ-EasyFPGA A2.1 had the following pinout on the page. I paid about 35$ and it took maybe 3 weeks to get here from china.

It came with a usb blaster programmer. and some usb cables. It can be powered from usb or from a 5 volt supply. I also got a camera.

This is better than the cyclone II chip I had before. More logic units, and I can use the newest version of Quartus II 16.1.  I like having some accessories on board




So I have a couple boards now.

Make a new project. Select Cyclone IV E series. EP4CE6E22C8 is the right chip. EP4CE6E22C8N is what the seller says. What does the N mean?

Here is a very simple counter. The clk is 50Mhz clock so I attached bits 25 to the leds in the pin assignment. That should be slow enough for me to see.

make a new verilog file with the same name as the project. This is the top level design file

module blinkcyclone4    (
out     ,  // Output of the counter
clk     ,  // clock Input


    output [25:0] out;
//------------Input Ports--------------
     input  clk;
//------------Internal Variables--------
    reg [25:0] out;
//-------------Code Starts Here-------
always @(posedge clk)
  out <= out + 1;




In the programmer window select the .sof file in the output folder .

Works. Sweet.

Now let’s try getting those LED digits up

Useful reference

The Dig signal needs to be clocked? It probably accepts on a positive edge or something. No. The dig signal is active low. I probably need to have the thing cycle through really fast. There is probably no memory in the led unit


The display is inverted. 0 is on and 1 is off

module led_test    (

input clk     ,  // clock Input
output segA, segB, segC, segD, segE, segF, segG, segDP,
output dig1, dig2, dig3, dig4


//wire [3:0] dig;
//assign {dig1,dig2,dig3,dig4} = dig;
assign dig1 = 1'b0;//clk;//1'b1;
assign dig2 = 1'b1;

//reg [25:0]cnt;
//assign dig = cnt[25:22];

//always @(posedge clk) cnt <= cnt+1;

assign {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b00100101; //8'b11011010;   // light the leds to display '2'


This should print a 2 on the first digit.


I went to opencores and got a simple UART core

Put it in the project directory. Add all the files to the porject. Make the loopback example the top level design by right clicking,simple_uart_for_fpga

Fired up arduino ide serial monitor. Yup. It’s looping back characters. Nice.







8 thoughts on “Some simple FPGA stuff”

  1. Hi,

    I am using Quatrus Prime Lite Edition. I need to make Pin Assignment for board. How did you do for this board RZ-EasyFPGA A2.1 ?

    How did you used it with Altera Quatrus Prime Lite Edition

  2. Hi Kalpesh, it looks like I got here a year too late, but for anyone else, here are the steps I took to get the board to work.

    To make these steps more readable, try copy/pasting them into a online markdown editor (like I hope that works.


    # Using
    * FPGA Development Board: RZ-EasyFPGA A2.2 from AliExpress, featuring the Altera Cyclone IV.
    * OS: Ubuntu 18.04 LTS (bionic)

    # Quartus Installation
    1. Get the Quartus Lite installer, ModelSim installer (optional), and the Cyclone IV development Package from the Altera website.
    — Get it here:
    — You gotta click on Lite Edition > (Select version and OS) > Individual files and download: Quartus Prime (includes Nios II EDS) and Cyclone IV device support. Files are about 500MB – 2000MB.
    2. Install Quartus. Root not required. Command:
    $ chmod +x
    $ ./
    — Place in ~/.intelFPGA_lite/18.0 (Note the dot before ‘intel’).
    3. Try running Quartus and verify that it launches. Command: `~/.intelFPGA_lite/18.0/quartus/bin$ ./quartus`
    — If you get an error like ` cannot open shared object file: No such file or directory` then go to and download/install latest for ubuntu amd64. Example:
    $ wget -q -O /tmp/libpng12.deb
    $ sudo dpkg -i /tmp/libpng12.deb
    $ rm /tmp/libpng12.deb

    # Hello World Example
    1. Open Quartus.
    2. Create a new Project
    **2.1 File → New → New Quartus Prime Project**
    **2.2. General Settings:**
    2.2.1 Working directory should be ‘/helloWorld’.
    2.2.2 Set name and top-level-design entity to ‘HelloWorld’.
    2.2.3 Create an Empty Project
    2.2.4 For Design Files, add that Cyclone IV file you downloaded, cyclone- (or similar).
    **2.3 Family, Device and Board Settings**
    2.3.1 Family: Cyclone IV E
    2.3.2 Device: All
    2.3.3 Target Device: Specific device selected in ‘Available devices’ list.
    2.3.4 Name Filter: EP4CE6E22C8
    2.3.5 Select the EP4CE6E22C8, not the ‘EP4CE6E22C8L’.
    **2.4 EDA Tools Settings**
    — None for now but it would be nice to get ModelSim-Altera working for Simulation.
    3. You should now have a blank HelloWorld project staring at you.
    4. Add a main source file. Select File > New > Verilog HDL File. Name it ‘HelloWorld.v’ and save it.
    5. Add the following code to HelloWorld.v:
    module HelloWorld (
    input clk,
    output led1, led2, led3, led4

    reg [25:0] dig;

    // Custom order of LEDs to distinguish from default program
    assign {led1, led4, led3, led2} = dig[25:22];

    always @(posedge clk) dig Import Assignments’ and load up your text file to overwrite the assignment editor. (I couldn’t figure out how to do this through the Quartus editor). Your pin assignments should populate automatically.
    Compile the project again.
    9. Click on ‘Programmer’ to open the programmer window. Configure the programmer.
    — Hardware Setup: USB_blaster [3-2]
    — Mode: JTAG
    — File: (Select HelloWorld.sof, which should be the only option).
    — Make sure “Program/Configure” is checked.
    10. Make sure your development board is connected to power source, connected via USB-Blaster to PC, and turned on.
    11. Flash the circuit by clicking ‘Start’.
    12. The LEDs on the board should start doing a little jig, different from the standard clock sequence.

    # Troubleshooting
    When flashing to the board, you click Start and nothing happens. Start by running jtagconfig. (`peach@peach01:~/.intelFPGA_lite/18.0/quartus/bin$ ./jtagconfig`)
    ### Unable to lock chain – Insufficient port permissions
    1. Run solution here (
    2. Then, restart the JTAG daemon.
    sudo killall -9 jtagd
    3. Restart the PC.
    ### Unable to read device chain – JTAG chain broken
    In case you see this error message, your USB Blaster works, but you can’t to connect to the JTAG chain. A possible cause can be a missing 32 Bit version of libudev. Download libudev1:i368 and create a symbolic link.
    $ sudo apt-get install libudev1:i386
    $ sudo ln -sf /lib/x86_64-linux-gnu/ /lib/x86_64-linux-gnu/
    Another source also suggests you have the board powered on and USB Blaster connected to the board before hooking it up to the computer.
    The expected output is
    ~/.intelFPGA_lite/18.0/quartus/bin$ ./jtagconfig
    1) USB-Blaster [3-2]
    020F10DD 10CL006(Y|Z)/10CL010(Y|Z)/..

  3. Program the Cyclone IV with OpenOCD with Altera USB Blaster programmer. If you want to program the board with Rapsbery Pi.

    First you have to create a file named altera-usb-blaster_my.cfg
    —————————————- start here —————————————–
    # Altera USB-Blaster

    interface usb_blaster
    usb_blaster_lowlevel_driver ftdi
    # These are already the defaults.
    # usb_blaster_vid_pid 0x09FB 0x6001
    # usb_blaster_device_desc “USB-Blaster”

    # Slow speed to be sure it will work
    adapter_khz 1000

    jtag newtap auto0 tap -irlen 2 -expected-id 0x020f10dd

    ——————————— end file ———————————————————–

    The file test_cyclone_IV.sof has to be converted to a SVF file
    You can convert the SOF file to SVF format from the quartus programmer software or through a command line sentence

    # To use 25 MHz TCK, 3.3V supply, and verify option
    quartus_cpf -c -q 25MHz -g 3.3 -n v

    Later you can program your board in ARM systems with:

    openocd -f altera-usb-blaster_my.cfg -c init -c “svf test_cyclone_IV.svf” -c shutdown

    Enjoy it !!!

  4. I saw this site because its quite impossible to find pinouts on the internet for this board, but when i use the VGA pins my seven-segment display lights up, i have the A2.2

  5. I saw this site because its quite impossible to find pinouts on the internet for this board, but when i use the VGA pins my seven-segment display lights up, i have the A2.2

  6. Hi, have you ever tried to get the onboard SDRAM working? I am experimenting for days and week now but I can’t get it working correctly. Would appreciate some help. Thanks and kind regards, Roland

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