See Also:

  • compilers
  • computer architecture
  • operating systems
  • assembly
  • parallel
  • concurrency
  • ebpf
  • fuzzing


I mean. This is the whole name of the game really. All my favorite tracing tools: eBPF, QEMU, Perfetto, new ones I built and more - Tristan Hume

Intel PT ebpf

Estimating Maximum Possible Perf

If compute bound: Single core freq ~3Ghz * 8 byte words -> 24Gb/s RAM SSD speeds - look it up. sequential vs no nsequential v different. Maybe ~1 gb/s as a order of magnitude


latency numbers every programmer should know napkin math estimating memory bandwidth

What kind of stuff is in my cpu. How to estimate various parameters.

lscpu -C # cache
#L1d       48K     192K   12 Data            1   64        1             64
#L1i       32K     128K    8 Instruction     1   64        1             64
#L2       512K       2M    8 Unified         2 1024        1             64
#L3         8M       8M   16 Unified         3 8192        1             64

lscpu -e
#  0    0      0    0 0:0:0:0          yes 3900.0000 400.0000 1500.000
#  1    0      0    1 1:1:1:0          yes 3900.0000 400.0000 1500.000
#  2    0      0    2 2:2:2:0          yes 3900.0000 400.0000 1500.000
#  3    0      0    3 3:3:3:0          yes 3900.0000 400.0000 1500.000
#  4    0      0    0 0:0:0:0          yes 3900.0000 400.0000 1500.000
#  5    0      0    1 1:1:1:0          yes 3900.0000 400.0000 1500.000
#  6    0      0    2 2:2:2:0          yes 3900.0000 400.0000 2719.516
#  7    0      0    3 3:3:3:0          yes 3900.0000 400.0000 2873.892

#  Address sizes:         39 bits physical, 48 bits virtual
# Vulnerabilities. That's ineresting my cpu Max 55.63 GiB/s Bandwidth Single 13.91 GiB/sDouble 27.82 GiB/sQuad 55.63 GiB/s

Instruction Level Parallelism (ILP)

SIMD Designing a SIMD Algorithm from Scratch

Filtering a vector with simd - rust

art of simd - slotkin Minotaur: A SIMD-Oriented Synthesizing Superoptimizer HACLxN: Verified Generic SIMD Crypto (for all your favourite platforms) compressed bitmaps

Simd for C++ developers

What this? roaring bitmaps simdjson judy arrays People are mentioned warming up the branch predictors on purpose somehow Branchless programming

#include <chrono>
#include <thread>
#include <vector>
#include <cstdint>
#include <iostream>

volatile size_t g_sum = 0;
__attribute__ ((noinline))
uint64_t sum(const uint8_t *data, size_t start, size_t len, size_t skip = 1) {
    uint64_t sum = 0;
    for (size_t i = start; i < len; i+= skip) {
        sum += data[i];
    g_sum += sum;
    return sum;
" intel memory latency checker


See also note on memory-management

dhat check for memory allocation sites that are worst Can use vector to store fixed size chunks. Your own private malloc specialized for one size

memory overhead. Probably Powers of two. But allocator may have “slop” can lose a lot of memory that way

What every programmer should know about memory

RAM - DDR double data rate. read cycle time - time between reads tosame row CAS latency - time from column to recieving data

RAS, CAS, WE bits select command type

Cache lines - 64 bytes. Even if you read/write 1 byte you’re writing 64


Power profiling is determining what is using electricity / battery life up. Very relevant to my common problem with my laptop dying


Hmm. wifi is using a lot of power

intel_atomic_commit - huh. is this actually correlated with touching the touchpad?

nic:docker0 is using a lot. sudo systemctl disable docker.service sudo ifconfig docker0 down sudo ifconfig br-557a6ccfc9fc down

A mysterious br-something device is usng like 5W of power. INternet still works if I turn that off



Page how to allocate huge tables



Performance matters, it unlocks new applications, important for business python -> avx extensions: x60,000 in one example Measurement is really important and hard. CPU can overclock for a little bit. Try to control the environment

Use statistical tests to determine if real change. student t for example Plot your benchmark data. Bimodal? Two different behaviors are happening microbenchmarks: be careful. Is it inlining a bunch of stuff? Anything except your exact final application and environment is a proxy. That the proxy at all represents the real behavior is fishy. Never forget that. System clock and system counters.

Agner Fog

manual 1

Reduce data dependencies a[i++] may be faster than a[++i] because of a data dependency reduction bool in C++ outputs 0/1 but may have come from a source that didn’t. This means it needs branching code for simple satuff short circuiting && ||, try to short circuit early

Stuff Performance-portable, length-agnostic SIMD with runtime dispatch

rust perf book

Intel PT LBR

1 billion row challenge 1brc remoe java unsafe

criterion use cachegrind for stable measurements in CI benchamrking commandline programs timeline over git commit

casey muratori series

cp algorithms competitive programming algorithsm

geoff langdale blog

iterating over set bits

Computing Adler32 Checksums at 41 GB/s

how fast are linux pipes anyway pv - pipe viewer. pipe thorughput

really cool blog posts

Software pipelining

The Art of Writing Efficient Programs: An advanced programmer’s guide to efficient hardware utilization and compiler optimizations using C++ examples - Pikus

Given the potential for straightline speculation w/ deleterious performance impact, does it makes sense to align functions with speculation blocking instructions like INT3 instead of nops? microbenchmarks of return address prediction (ras)

programming parallel computers course asm("# foo"); nice trick. Inject comment into assembly

fread vs mmap Rough advice: fread is simple and often comparable to mmap (system dependent). mmap can sometimes be up to 4x faster, use madvise, weird exceptions/signals need to be handled.

performance tuning on linux - cromwell

dan luu new cpu features

Parsing series of integers with SIMD This Wojciech Muła guy is a wizard

unaligned vector load + length-driven PSHUFB. What’s everyone’s favourite way to handle page crossings? overreading for short variables possibly into out of bounds memory? pshufb

umash very fast hash Algorithms for Modern Hardware - book on algorithms on modern hardware

CLMUL fast instruction set for galois field calculations. carryless

x86 instrinsic cheatsheet

OSACA an analyzer of assembly code. It is on godbolt

This gruop has a number of interesting tools. It scrapes info from

  • Likwid
  • kerncraft loop kernel analysis and performance modelling

List of interesting optimizers - These are compiler optimizations, so hopefully your compiler does them for you, but maybe it doesn’t and maybe Lemire converting integerrs to fix digit representations By considering data dependencies and using lookup tables take from 25ns to 2ns.

MIT optimization course surprising subtleites of zeroing a register. agner fog optimization manuals memset and memcpy ooptimizations Go does not need a garbage collector. Compares and contrasts java GC with others. Claims Java poorly designed make high pressure on GC intel opimization manual mimalloc- de moura, daan leijen, ben zorn

I feel like most algorithms and data structures are os ordinary they are kind of boring?

Sparse Sets - knuth - bitvectors + Bitvectors ullmann bitvector algos for binary constraint and subgraph iso.

Books: CLRS

Sorting algorithms Hash tables Dynamic programming Tries Graph algorithsm - shortest path, spanning tree hash table in C. some interesting commments too linear search - an assoc list but he kept it in an array - hashing from z3 source code

lkinear probing vs linked list in hash table.

concurrent hash map Interesting. Cache-oblivious binary search. Uses the “Heap” ordering or what have you Plus a branchless comparator? I think also a big point is How do you even know when cache something is a problem. How do you use feedback and self correct? How do you organize tight loops? “smart” ways of keeping structure.

microbenchmarking performance counters - cache misses, TLB ht/miss, mispredicted branches nanobench VTune, perf, PAPI, libpfc,

What every programmer should know abouyt memory

modern microprcessor 90 minute guide Bentley Writing Efficient Program - a rust optimization story - handmade hero guy talkin about optimizations - refterm optimization talk. this is fascinating

  1. optimization - measuring.
  2. non-pessimization - don’t do unnecessary work
  3. fake optimziation - people just repeatin shit uica online demo gives info on what’s hurtin ya. Cycle counts and stuff microp_ops. Ports? Queue? DaY 112 of hnadmade hero. perf counter. simd. converting to simd. measuring port usage with iaca

perf seems balla. Works on ocaml btw - linux systems performance The gem5 simulator is a modular platform for computer-system architecture research, encompassing system-level architecture as well as processor microarchitecture gem5, MARSS×86 , Multi2Sim, PTLsim, Sniper, and ZSim. gem5 as an alternaitve to qemu?

NUMA - non uniform memory access register file? l1 cache. instruction and data. instruction is one way lstopo --no-io tells you how your computer looks large /huge pages. faster for TLB. Hugetablefs is linux suppotrt? /proc/cpuinfo Transparent Huge Pages- madvise is a call yes I’d like huge tables. defer cache lines - 64 bytes. even if you read/write 1 byte your’re writing 64 M exculsively own and dirty, E exlucsive and clean, S shared, , I invalid _builtin_prefecth. linear access is good splitting into revcord of arrays tends to be better for cache if only using one field. compressed memory is worth it. compuitayion is fast. memory is slow. Array of structs vs struct of arrays. Compressed pointers? pinning isolcpus boot time option. pinning of thread or memory to cpu taskset. linux admin styuff. isolate cpus to certain tasks numactl and libnuma loop stream decoder branch predictor, pipelikne stall or bubble. branch target predcitro ports, execution units. some logic, some airthmetic. perf - interrogate counters. record report annotate stat skid - bad - precision knobs :p :pp :ppp perf record -b perf record –call-graph lbr -j any_call,any_ret program -e intel_pt//u LBR - last branch record - linux weekly intel processors record control flow Intel processor trace IPC - intrcutions per cycle. 4 is maximum ish. less than 1 is perf stat performance ocunters - perf -list TMAM top down microarctecture analsyis method perf -dtopdown toplev go throgyh process. and kleen. fancy frontend to perf/ -l1 l2 __builtin_expect profile guided optimization may do builtin expect for you loop alginment - 32 bit boundaries. straight from uop cache. llvm flag. align-all-nofallthru-blocks align-all-function code alignment can changed your perfoamnce. BOLT - vinary optimization layout tranformer. defrag your code. Puts hot code in same memory location at runtime Daniel Lemire - simd parser. mechnisms for avodiing branching. masking operations. Summary - cache aligned / cache aware data structures. B-trees. Compress data. Avoid random memory access. Huge pages can help. 10% speedup by enabling maybe. libnuma source memory. branch0free and lock-free. perf /toplev. Use vectorization where you can. his blog reference links


Blog links neato: nethrcote blog