Using EDA Playground

So to write Verilog code you need to write a testbench.

The #10 type things are delays.

The dumpfile thing is needed by edaplayground

The reset logic was necessary or else the submodule had unspecified values

Make sure to check the open EPWave box on the side

Everything needs to be wrapped in a module endmodule.

The .clk is specifying the parameter. the clk inside the parentheses is the reg I’m passing it.

I set reset high. Wait, then turn it low.

To end the simulation you need the $finish command.


specify how this module can connect to the outside world

<= is some kind of sequential assignment. It tends to be what is used in these posedge type blocks.

= is used to form aliases using the assign command

If else stuff is fairly self explanatory

begin end are the equivalent of {} in other languages


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