Single Bit Quantization

I’d heard that pifm, the raspberry pi radio pin thing used 1-bit quantization techniques. I was wondering what they were.

The basic idea of no free lunch states that you can trade the very high speed excess of a fast digital circuit for more effective bit depth of reconstruction.

A natural technique is pulse width modulation, but then you need an integration stage. Low pass filtering elements are more common. Sigma-Delta conversion is a technique that pushes quantization noise into higher frequencies such that a low pass filter will reconstruct the signal well. Pins natural have capacitance so you might get a low pass filter with no external circuitry at all if you’re going really ghetto.

I did some things with dithering and Sigma-delta in python. Interesting.

https://github.com/philzook58/python/blob/master/python/Sigma_Delta_Quantization.ipynb

Some scattered thoughts:

When sampling a signal into the digital world, you have to break it up into finite discrete chunks.

This distorts the thing. Question is how much and how should you do it?

http://repository.upenn.edu/cgi/viewcontent.cgi?article=1144&context=ese_papers

The simplest scheme is to break the signal up into expected intervals and count them off.

This does not get all out of the signal.

One model for discussing this is quantization noise. We can assume that the error introduced is uncorrelated with the input and is just additive noise.

If it’s quantized in steps of \Delta

\Delta

6n dB. For n bits be get another 6n of signal to noise.

http://www.cs.tut.fi/sgn/arg/rosti/1-bit/

 

Update: This seems like an interesting resource to dig into

http://www.python-deltasigma.io/

Some simple FPGA stuff

 

Some articles and links of interest

 

State Machines

Becoming a State Machine Design Mastermind

Verilog IceStorm Series

Learning Verilog for FPGAs: The Tools and Building an Adder

Learning Verilog for FPGAs: Flip Flops

Opencores UART and PWM

Taking the Pulse (Width Modulation) of an FPGA

FPGA in C

Xilinx FPGAs in C for Free

Bitonic Sort on FPGA

Sort Faster with FPGAs

FPGA motion planning

Manipulators get a 1000x FPGA-based speed bump

Gravity

Gravity Simulations With An FPGA

The seller of the Cyclone IV RZ-EasyFPGA A2.1 had the following pinout on the page. I paid about 35$ and it took maybe 3 weeks to get here from china.

It came with a usb blaster programmer. and some usb cables. It can be powered from usb or from a 5 volt supply. I also got a camera.

This is better than the cyclone II chip I had before. More logic units, and I can use the newest version of Quartus II 16.1.  I like having some accessories on board

 

 

fpga_pin_map

So I have a couple boards now.

Make a new project. Select Cyclone IV E series. EP4CE6E22C8 is the right chip. EP4CE6E22C8N is what the seller says. What does the N mean?

Here is a very simple counter. The clk is 50Mhz clock so I attached bits 25 to the leds in the pin assignment. That should be slow enough for me to see.

make a new verilog file with the same name as the project. This is the top level design file

 

 

In the programmer window select the .sof file in the output folder .

Works. Sweet.

Now let’s try getting those LED digits up

http://fpga4fun.com/Opto3.html

Useful reference

The Dig signal needs to be clocked? It probably accepts on a positive edge or something. No. The dig signal is active low. I probably need to have the thing cycle through really fast. There is probably no memory in the led unit

 

The display is inverted. 0 is on and 1 is off

 

This should print a 2 on the first digit.

 

I went to opencores and got a simple UART core

Put it in the project directory. Add all the files to the porject. Make the loopback example the top level design by right clicking

https://opencores.org/project,simple_uart_for_fpga

Fired up arduino ide serial monitor. Yup. It’s looping back characters. Nice.